library ieee;
use IEEE.STD_LOGIC_TEXTIO.all;
use STD.TEXTIO.all;
use ieee.std_logic_1164.all;


entity tb_VarLatRAM is
	generic (Period : Time := 100 ns;
           Debug : Boolean := False);
end tb_VarLatRAM;

architecture testbench_arch of tb_VarLatRAM is
	
	-- component(s)
  component VarLatRAM port (
								nReset          : in std_logic ;
                clock           : in std_logic ;
                address         : in std_logic_vector (15 DOWNTO 0);
                data            : in std_logic_vector (31 DOWNTO 0);
                wren            : in std_logic ;
                rden            : in std_logic ;
                latency_override: in std_logic ; 
                q               : out std_logic_vector (31 DOWNTO 0);
                memstate        : out std_logic_vector (1 DOWNTO 0) );
  end component;
	
	-- signals
  signal clk, nReset, done	: std_logic;
  signal wren, rden, latency_override : std_logic;
  signal data, q : std_logic_vector(31 downto 0);
  signal memstate : std_logic_vector(1 downto 0);
  signal address : std_logic_vector(15 downto 0);
	
	-- constants
  constant zero_v : std_logic_vector := x"00000000";
  constant data1_v : std_logic_vector := x"DEADBEEF";
  constant data2_v : std_logic_vector := x"60FA57E4";
	
	-- print procedures
  procedure println( output_string : in string ) is
    variable lout                  :    line;
  begin
    WRITE(lout, output_string);
    WRITELINE(OUTPUT, lout);
  end println;

  procedure printlv( output_bv : in std_logic_vector ) is
    variable lout              :    line;
  begin
    WRITE(lout, output_bv);
    WRITELINE(OUTPUT, lout);
  end printlv;


begin

	-- DUT
  DUT : VarLatRAM
  	port map (
  		nReset           =>	nReset,
      clock            =>	clk,
      address          =>	address,
      data             =>	data,
      wren             =>	wren,
      rden             =>	rden,
      latency_override =>	latency_override,
      q                =>	q,
      memstate         =>	memstate
		);

	-- generate clock signal
  clkgen: process
    variable clk_tmp : std_logic := '0';
  begin
    clk_tmp := not clk_tmp;
    clk <= clk_tmp;
    wait for Period/2;
  end process;
	
	-- TESTER
  process
  begin
  	done <= '0';
    println("");
    println("Starting Test");
    -- reset
    nReset <= '0';
    latency_override <= '0';
    wait for Period/2;
    nReset <= '1';
    rden <= '0';
    wren <= '0';
    address <= x"0000";
    data <= data1_v;

    wait for 1 ns;
    
    
    -- test here
    address <= x"0000";
    data <= data1_v;
    rden <= '1';
    wren <= '0';
    wait for Period*9;
    --wait for Period/2;
    rden <= '0';

    --wait for Period;

    wren <= '1';
    wait for Period*9;
    --wait for Period/2;
    wren <= '0';

    --wait for Period;

    rden <= '1';
    wait for Period*9;
    --rden <= '0';

    --wait for Period;
    --rden <= '1';
    address <= x"0004";
    

    println("Test Complete");
    println("");
    -- end simulation
    done <= '1';
    wait;
  end process;
  
end testbench_arch;


